Data security/correction devices are widely used to write data in memories, particularly electrically erasable and programmable memories of the EEPROM or FLASH EEPROM type. Data is secured when saved in the memory by adding security bits, and the data is corrected as a result of the security bits when read.
Moreover, data is traditionally coded before being saved in a memory when a certain level of confidentiality is required, and the data is decoded when the memory is read. Coding is defined to mean coding a binary word by a scrambling function to obtain a coded word. Therefore, sometimes combining a coding function and a security function in a single device is required to obtain from initial data a secured coded data entry, i.e., a binary word having undergone a double coding and security process.
FIG. 1 represents in block form a prior art data security/correction device ECC1. The device ECC1 comprises a data security circuit WR1 and a data correction circuit RD1. The circuit WR1 has one input IN1 to receive a binary word X1, and one output OUT1 to deliver a secured word X2. The circuit RD1 has one input IN2 to receive the secured word X3 having an error E, and one output OUT2 to deliver a corrected word X4.
The circuit WR1 comprises a block B1 that applies a function G to the word X1, and delivers the secured word X2. The function G is a security bit generation function that can be represented in the form of a matrix of (2K) lines and (2K+J) columns. By representing the binary word X1 in the form of a vector of 2K bits, the secured word X2 obtained complies with the following relation:X2=X1*G=DATA(X2)//CODE(X2).
The symbol * represents a matrix product, // is a symbol for concatenation (i.e., linking together in series or in a chain), DATA(X2) is a first part of the word X2 comprising 2K data bits, and CODE(X2) is a second part of the word X2 comprising J security bits.
The function G does not change the data bits of the initial word X1, such that the word DATA(X2) comprises data bits equal to those of the initial word X1. Therefore, the following can be written:X2=X1//CODE(X2).
As an example, it will be assumed that only one bit is to be detected and corrected in a word of eight bits by the Hamming algorithm. According to this algorithm, the number J of security bits must be equal to K+1 to detect and correct only one error bit in a word of 2K bits. Therefore, in this example, K=3 and J=K+1=4 and the words X1, X2 are written as described in part 1 of the supplemental information, which follows the detailed description. The function G is a matrix of 2K lines and (2K+K+1) columns, i.e., 8 lines and 12 columns, as described in part 2 of the supplemental information. The matrix G generates 4 security or parity bits p0, p1, p2, p3 as described in part 3 of the supplemental information.
It is now assumed that the secured word X2 is saved in a memory MEM, and that it is then read in that memory. Between the writing of the word and the moment it is read, the word is likely to be altered, which results in the word having an error. Such an error, statistically speaking, is quite frequent with electrically erasable and programmable memories of the EEPROM or FLASH EEPROM type. This is generally due to a defect affecting a floating-gate transistor of a memory cell (for example, a drift of its threshold voltage), or to a connection defect of a bit line or of a word line, etc.
To distinguish the word read from the initial secured word X2 that is presumed to be free from any error, the word read in the memory is called X3 and is considered equal to the sum of the word X2 and an error E:X3=X2+E
The symbol + is the bit to bit addition without carrying the sum forward, and E is a word of 2K+J bits representing the error affecting the word X2. This error may possibly be zero.
The word X3 and the error E can also be written as:X3=DATA(X3)//CODE(X3)E=ERR1//ERR2.
DATA(X3) is a word comprising 2K data bits, CODE(X3) is a word comprising J security bits, ERR1 is a word representing the error on the data bits formed by the 2K first bits of the error E, and ERR2 is a word representing the error on the security bits formed by the J following bits of the error E. The result is:DATA(X3)=DATA(X2)+ERR1=X1+ERR1CODE(X3)=CODE(X2)+ERR2.
The symbol + is the bit to bit addition without carrying the sum forward. For a better understanding, and using the example mentioned above (2K=8 and J=4), the words E, ERR1, ERR2, DATA(X3), CODE(X3) are written as mentioned in part 4 of the supplemental information.
The correction of the word X3 incorporating the error E (that can be zero) is carried out by the circuit RD1. This circuit comprises an error correcting block B2, a syndrome or pattern generator block B3, and an error vector generator block B4.
The block B2 has two inputs E1, E2 for receiving 2K bits each, and one output for providing 2K bits. The input E1 receives the data bits of the word X3, i.e., the word DATA(X3). The input E2 receives an error vector EV delivered by the block B4. The block B2 delivers a corrected word X4 that is equal to the initial word X1 provided that the effective error concerns a number of bits lower than or equal to the maximum number of bits that can be detected and corrected.
The word X4 is obtained by the logic combination of the word DATA(X3) and of the vector EV. This logic combination is generally done by the EXCLUSIVE OR function (xor function, symbol ⊕).
The block B3 receives the word X3 at an input, applies a function H to the word X3, and delivers a pattern SYN such that:SYN 32 X3*HSYN=(X2+E)*HSYN=(X1*G+E)*HSYN=X1*G*H+E*HSYN=E*HThe functions H and G are orthogonal functions and their product G*H is equal to 0.
With the Hamming algorithm, the function H is a matrix of (2K+K+1) lines and (K+1) columns, orthogonal at G. For a better understanding, such a matrix H is described in part 5 of the supplemental information, in which K=3 and J=4. This matrix H generates a pattern SYN of four bits S0, S1, S2, S3 allowing one error per word to be detected and corrected. The logic value of the bits S0 to S4 is described in part 6 of the supplemental information.
The pattern SYN is applied to the block B4 that performs a pattern/vector conversion function EV=f(SYN), and delivers an appropriate vector EV. This pattern/vector conversion function conforms to a predetermined table of correspondence. For a better understanding, a pattern/vector table of correspondence is described in part 7 of the supplemental information, in which K=3 and J=4.
In theory each error vector EV comprises one part EV1 and one part EV2, and can be writtenEV=EV1//EV2EV1 is an error vector of 2K bits representing an error on the data, and EV2 is an error vector of J bits representing an error on the security bits. In practice, error correcting on the security bits is pointless, and only the error vector EV1 is delivered by the block B4 and is applied to the input E2 of the block B2.
The error vector EV is equal to the error E itself when the block B2 performs the EXCLUSIVE OR function. In fact:DATA(X3)⊕(EV1=X1However:DATA(X3)⊕EV1=X1+ERR1⊕EV1which gives:ERR1⊕EV1=0which implies that:ERR1=EV1The symbol + is the bit to bit addition without carrying the sum forward, and ⊕ is the EXCLUSIVE OR function.
FIG. 2 represents a device ECC2 that differs from the device ECC1 by the fact that it comprises, in addition, coding and decoding means, which forms a data coding/decoding and security/correction device.
The device ECC2 comprises a data coding and security circuit WR2, and a data decoding and correction circuit RD2. The circuit WR2 has one input IN1 to receive a binary word X0, and one output OUT1 to deliver a secured code word X2. The circuit RD2 has one input IN2 to receive a secured code word X3 having an error E (that can be zero), and one output OUT2 to deliver a corrected decoded word X5.
The circuit WR2 comprises in series one block B0 and the block B1 described above. The input of the block B0 receives at one input the word X0, applies a coding function A to the word X0 and delivers a code word X1 to one input of the block B1. The block B1 applies to the word X1 the function G already described, and delivers the word X2 to the output OUT1 of the circuit WR2. An example of the coding function A is described in part 8 of the supplemental information, in the form of a matrix of 2K lines and 2K columns, in which K=3.
It will now be considered as above that the word X2 is stored in a memory MEM, and the word read subsequently in the memory shall be designated X3, with X3 being equal to the word X2 to which the error E is added. The correction of the error E and the decoding of the word X3 are carried out by the circuit RD2. The latter differs from the circuit RD1 of the device ECC1 by the fact that a decoding block B5 is arranged between the output of the block B2 and the output OUT2. The block B5 applies a decoding function A−1 that is the reciprocal of the function A to the data received at its input. An example of the decoding function A−1 is described in part 9 of the supplemental information. The function A−1 is an inverse matrix of the matrix A described in part 8 of the supplemental information.
The operation of the device ECC2 is therefore as follows. The block B0 generates a code word X1 from the initial word X0. The block B1 generates a secured code word X2 from the code word X1. The block B2 carries out an error correction on a secured code word X3, and delivers a corrected code word X4. The block B5 carries out the decoding of the corrected code word X4 and delivers a corrected decoded word X5. The blocks B1, B3 and B4 are identical to those of the device ECC1, since the word X1 is a code word that has no impact on the security and the correction of this word.
The circuits ECC1 and ECC2 that have just been described are traditionally formed from hard-wired logic blocks. The conversion time of the word X1 into the word X2 (security) and the conversion time of the word X3 into the word X4 (correction) therefore directly varies according to the data propagation time in the logic gates present along the data path between the input IN1 and the output OUT1 and between the input IN2 and the output OUT2.
The drawback of the device ECC2 is that the data transfer process is slowed down by the addition of the blocks B0 and B5 along the data path. The blocks B0 and B5 are in fact, like the blocks B1 to B4, and are produced using logic gates and have a determined data transfer time. The addition of the blocks B0 and B5 can increase by 30 to 50% the data transfer time between the inputs and the outputs of the device ECC2, as compared to the device ECC1.